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freescale semiconductor data sheet: advance information document number: mcf51qe128 rev. 3, 06/2007 ? freescale semiconductor, inc., 2007. all rights reserved. this document contains information on a new pro duct. specifications and information herein are subject to change without notice. mcf51qe128 ? 32-bit version 1 coldfire ? central processor unit (cpu) ? up to 50.33-mhz coldfire cpu from 3.6v to 2.1v, and 20-mhz cpu at 2.1v to 1.8v across temperature range of -40c to 85c ? provides 0.94 dhrystone 2.1 mips per mhz performance when running from internal ram (0.76 dmips/mhz from flash) ? implements instruction set revision c (isa_c) ? support for up to 30 peripheral interrupt requests and seven software interrupts ?on-chip memory ? flash read/program/erase over full operating voltage and temperature ? random-access memory (ram) ? security circuitry to prev ent unauthorized access to ram and flash contents ? power-saving modes ? two low power stop modes; reduced power wait mode ? peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode ? very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals ? very low power real time counter for use in run, wait, and stop modes with internal and external clock sources ?6 s typical wake up time from stop modes ? clock source options ? oscillator (xosc) ? loop- control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? fll controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports cpu freq. from 2 to 50.33 mhz ? system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1-khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode and illegal address detection with programmable reset or exception response ? flash block protection ? development support ? single-wire background debug interface ? 4 pc plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response ? 64-entry processor status and debug data trace buffer with programmable start/stop conditions ? adc ? 24-channel, 12-bit resolution; 2.5 s conversion time; automatic comp are function; 1.7 mv/ c temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6v to 1.8v ? acmpx ? two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to tpm module; operation in stop3 ? scix ? two scis with full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge ? spix? two serial peripheral interfaces with full-duplex or single-wire bidirectional; double-buffered transmit and receive; msb-first or lsb-first shifting ? iicx ? two iics with; up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing ? tpmx ? one 6-channel and two 3-channel; selectable input capture, output compar e, or buffered edge- or center-aligned pwms on each channel ? rtc ? 8-bit modulus counter with binary or decimal based prescaler; external cl ock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components ? input/output ? 70 gpios and 1 input-only and 1 output-only pin ? 16 kbi interrupts with selectable polarity ? hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output pins. ? set/clr registers on 16 pins (ptc and pte) ? 16 bits of rapid gpio connected to the cpu?s high-speed local bus with set, clear, and toggle functionality 80-lqfp case 917a 14 mm 2 64-lqfp case 840f 10 mm 2 mcf51qe128 series covers: mcf51qe128, MCF51QE64
mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 2 table of contents 1 mcf51qe128 series comparison . . . . . . . . . . . . . . . . . . . . . .4 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .9 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 3.5 esd protection and latch-up immunity . . . . . . . . . . . .11 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.7 supply current characteristics . . . . . . . . . . . . . . . . . . .15 3.8 external oscillator (xosc) characteristics . . . . . . . . .18 3.9 internal clock source (ics) characteristics . . . . . . . . .19 3.10 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.10.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.10.2 tpm module timing . . . . . . . . . . . . . . . . . . . . . 23 3.10.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.4 analog comparator (acmp) electricals . . . . . . 27 3.10.5 adc characteristics. . . . . . . . . . . . . . . . . . . . . 27 3.10.6 flash specifications . . . . . . . . . . . . . . . . . . . . . 30 3.11 emc performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.11.1 radiated emissions . . . . . . . . . . . . . . . . . . . . . 31 3.11.2 conducted transient susceptibility . . . . . . . . . 31 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 3 figure 1. mcf51qe128 series block diagram tpm2ch2-0 tpm1ch2-0 analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic1) serial peripheral interface module (spi1) user flash user ram 128k / 64k v1 coldfire core cpu bdc / debug 6-channel timer/pwm module (tpm3) system control resets and interrupts modes of operation power management voltage regulator cop - lvd oscillator (xosc) reset v refl v refh 8k / 6k / 4k bkgd/ms interface (sci1) serial communications miso1 ss1 spsck1 3-channel timer/pwm module (tpm2) real time counter (rtc) rapid gpio irq pta3/kbi1p3/scl1/adp3 pta4/acmp1o/bkgd/ms pta5/irq/tpm1clk/reset pta2/kbi1p2/sda1/adp2 pta1/kbi1p1/tpm2ch0/adp1/acmp1- pta0/kbi1p0/tpm1ch0/adp0/acmp1+ port a pta6/tpm1ch2/adp8 pta7/tpm2ch2/adp9 mosi1 ptb3/kbi1p7/mosi1/adp7 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptb2/kbi1p6/spsck1/adp6 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 port b ptb6/sda1/xtal ptb7/scl1/extal ptc3/rgpio11/tpm3ch3 ptc4/rgpio12/tpm3ch4/rsto ptc5/rgpio13/tpm3ch5/acmp2o ptc2/rgpio10/tpm3ch2 ptc1/rgpio9/tpm3ch1 ptc0/rgpio8/tpm3ch0 port c ptc6/rgpio14/rxd2/acmp2+ ptc7/rgpio15/txd2/acmp2- ptd3/kbi2p3/ss2 ptd4/kbi2p4 ptd5/kbi2p5 ptd2/kbi2p2/miso2 ptd1/kbi2p1/mosi2 ptd0/kbi2p0/spsck2 port d ptd6/kbi2p6 ptd7/kbi2p7 pte3/rgpio3/ss1 pte4/rgpio4 pte5/rgpio5 pte2/rgpio2/miso1 pte1/rgpio1/mosi1 tpm2clk port e pte6/rgpio6 pte0/rgpio0/tpm2clk/spsck1 ptf3/adp13 ptf4/adp14 ptf5/adp15 ptf2/adp12 ptf1/adp11 ptf0/adp10 port f ptf6/adp16 ptf7/adp17 ptg1 ptg2/adp18 ptg3/adp19 port g ptg4/adp20 ptg5/adp21 ptg0 v ss v dd v ssa v dda ip bus bridge intc analog comparator (acmp2) interface (sci2) serial communications tpm3ch5-0 ptg6/adp22 ptg7/adp23 source (ics) internal clock port j port h ptj1 ptj2 ptj3 ptj4 ptj5 ptj0 ptj6 ptj7 pth1 pth2 pth3 pth4 pth5 pth0 pth6/scl2 pth7/sda2 iic module (iic2) analog-to-digital converter (adc) 24-channel,12-bit 3-channel timer/pwm module (tpm1) sda2 scl2 serial peripheral interface module (spi2) miso2 ss2 spsck2 mosi2 extal xtal 16 sda1 scl1 acmp2- acmp2+ acmp2o rxd1 txd1 rxd2 txd2 tpm3clk 3 tpm1clk pte7/rgpio7/tpm3clk
mcf51qe128 series advance information data sheet, rev. 3 mcf51qe128 series comparison freescale semiconductor 4 1 mcf51qe128 series comparison the following table compares the various device derivatives available within the mcf51qe128 series. table 1. mcf51qe128 series features by mcu and package feature mcf51qe128 MCF51QE64 flash size (bytes) 131072 65536 ram size (bytes) 8192 4096 pin quantity 80 64 64 version 1 coldfire core yes acmp1 yes acmp2 yes adc channels 24 22 22 dbg yes ics yes iic1 yes iic2 yes kbi 16 port i/o 1, 2 1 port i/o count does not include the input-only pta5/irq/tpm1clk/reset or the output-only pta4/acmp1o/bkgd/ms. 2 16 bits associated with ports c and e are shadowed with coldfire rapid gpio module. 70 54 54 rapid gpio yes rtc yes sci1 yes sci2 yes spi1 yes spi2 yes external irq yes tpm1 channels 3 tpm2 channels 3 tpm3 channels 6 xosc yes
pin assignments mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 5 2 pin assignments this section describes the pin assign ments for the available packages. see table 1 for pin availability by package pin-count. figure 2. pin assignments in 80-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v refh v ssad v dd v refl v ddad v ss ptb7/scl1/extal pth7/sda2 ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 pte6/rgpio6 ptb6/sda1/xtal pth6/scl2 pte7/rgpio7/tpm3clk pth1 pth0 pth3 pth2 pth5 pth4 ptc2/rgpio10/tpm3ch2 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptc3/rgpio11/tpm3ch3 ptd7/kbi2p7 ptc0/rgpio8/tpm3ch0 ptc1/rgpio9/tpm3ch1 ptd6/kbi2p6 ptd5/kbi2p5 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 pte5/rgpio5 ptf7/adp17 ptf6/adp16 ptf5/adp15 ptf4/adp14 ptd4/kbi2p4 v dd v ss pta7/tpm2ch2/adp9 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda1/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2 pte4/rgpio4 ptf0/adp10 ptf1/adp11 ptf2/adp12 ptf3/adp13 pte2/rgpio2/miso1 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta0/kbi1p0/tpm1ch0/adp0/acmp1+ ptc7/rgpio15 /txd2/acmp2- ptc5/rgpio13/tpm3ch5/acmp2o ptc4/rgpio12/tpm3ch4/rsto ptc6/rgpio14/rxd2/acmp2+ pte0/rgpio0/tpm2clk/spsck1 pte1/rgpio1/mosi1 pte3/rgpio3/ss1 ptg3/adp19 ptg2/adp18 ptg1 ptg0 ptg7/adp23 ptg6/adp22 ptg5/adp21 ptg4/adp20 ptj4 ptj5 ptj6 ptj7 ptj1 ptj0 ptj3 ptj2 pta1/kbi1p1/tpm2ch0/adp1/acmp1- pins in bold are added from the next smaller package.
mcf51qe128 series advance information data sheet, rev. 3 pin assignments freescale semiconductor 6 figure 3. pin assignments in 64-pin lqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v refh v ssad v dd v refl v ddad v ss ptb7/scl1/extal pth7/sda2 ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 pte6/rgpio6 ptb6/sda1/xtal ptc2/rgpio10/tpm3ch2 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptc3/rgpio11/tpm3ch3 ptd7/kbi2p7 ptc0/rgpio8/tpm3ch0 ptc1/rgpio9/tpm3ch1 ptd6/kbi2p6 ptd5/kbi2p5 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 pte5/rgpio5 ptd4/kbi2p4 v dd v ss pta7/tpm2ch2/adp9 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda11/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2 pte4/rgpio4 pte2/rgpio2/miso1 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta0/kbi1p0/tpm1ch0/adp0/acmp1+ pta1/kbi1p1/tpm2ch0/adp1/acmp1- ptc7/rgpio15/txd2/acmp2- ptc5/rgpio13/tpm3ch5/acmp2o ptc4/rgpio12/tpm3ch4/rsto ptc 6/rgpio14/rxd2/acmp2+ pte0/rgpio0/tpm2clk/spsck1 pte1/rgpio1/mosi1 pte3/rgpio3/ss1 ptf0/adp10 ptf1/adp11 ptf7/adp17 ptf6/adp16 ptf5/adp15 ptf4/adp14 ptf2/adp12 ptf3/adp13 ptg3/adp19 ptg2/adp18 ptg1 ptg0 pth6/scl2 pte7/rgpio7/tpm3clk pth1 pth0
pin assignments mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 7 table 2. mcf51qe128 series pin assignmen t by package and pin sharing priority pin number lowest ? priority ? highest 80 64 port pin alt 1 alt 2 alt 3 alt 4 1 1 ptd1 kbi2p1 mosi2 2 2 ptd0 kbi2p0 spsck2 3 3 pth7 sda2 44 pth6 scl2 5? pth5 6? pth4 7 5 pte7 rgpio7 tpm3clk 86 v dd 97 v ddad 10 8 v refh 11 9 v refl 12 10 v ssad 13 11 v ss 14 12 ptb7 scl1 extal 15 13 ptb6 sda1 xtal 16 ? pth3 17 ? pth2 18 14 pth1 19 15 pth0 20 16 pte6 rgpio6 21 17 pte5 rgpio5 22 18 ptb5 tpm1ch1 ss1 23 19 ptb4 tpm2ch1 miso1 24 20 ptc3 rgpio11 tpm3ch3 25 21 ptc2 rgpio10 tpm3ch2 26 22 ptd7 kbi2p7 27 23 ptd6 kbi2p6 28 24 ptd5 kbi2p5 29 ? ptj7 30 ? ptj6 31 ? ptj5 32 ? ptj4 33 25 ptc1 rgpio9 tpm3ch1 34 26 ptc0 rgpio8 tpm3ch0 35 27 ptf7 adp17 36 28 ptf6 adp16 37 29 ptf5 adp15 38 30 ptf4 adp14 39 31 ptb3 kbi1p7 mosi1 1 adp7 40 32 ptb2 kbi1p6 spsck1 adp6
mcf51qe128 series advance information data sheet, rev. 3 pin assignments freescale semiconductor 8 41 33 ptb1 kbi1p5 txd1 adp5 42 34 ptb0 kbi1p4 rxd1 adp4 43 ? ptj3 44 ? ptj2 45 35 ptf3 adp13 46 36 ptf2 adp12 47 37 pta7 tpm2ch2 adp9 48 38 pta6 tpm1ch2 adp8 49 39 pte4 rgpio4 50 40 v dd 51 41 v ss 52 42 ptf1 adp11 53 43 ptf0 adp10 54 ? ptj1 55 ? ptj0 56 44 ptd4 kbi2p4 57 45 ptd3 kbi2p3 ss2 58 46 ptd2 kbi2p2 miso2 59 47 pta3 kbi1p3 scl1 2 adp3 60 48 pta2 kbi1p2 sda1 adp2 61 49 pta1 kbi1p1 tpm2ch0 adp1 acmp1- 62 50 pta0 kbi1p0 tpm1ch0 adp0 acmp1+ 63 51 ptc7 rgpio15 txd2 acmp2- 64 52 ptc6 rgpio14 rxd2 acmp2+ 65 ? ptg7 adp23 66 ? ptg6 adp22 67 ? ptg5 adp21 68 ? ptg4 adp20 69 53 pte3 rgpio3 ss1 70 54 pte2 rgpio2 miso1 71 55 ptg3 adp19 72 56 ptg2 adp18 73 57 ptg1 74 58 ptg0 75 59 pte1 rgpio1 mosi1 76 60 pte0 rgpio0 tpm2clk spsck1 77 61 ptc5 rgpio13 tpm3ch5 acmp2o 78 62 ptc4 rgpio12 tpm3ch4 rsto 79 63 pta5 irq tpm1clk reset 80 64 pta4 3 acmp1o bkgd ms table 2. mcf51qe128 series pin assignment by package and pin sharing priority (continued) pin number lowest ? priority ? highest 80 64 port pin alt 1 alt 2 alt 3 alt 4
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 9 3 electrical characteristics 3.1 introduction this section contains electrical and timing specifications for the mcf51qe128 series of microcontrollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 4 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. 1 spi1 pins (ss1 , miso1, mosi1, and spsck2) ca n be repositioned using spi1ps in sopt2. default locations are ptb5, ptb4, ptb3, and ptb2. 2 iic1 pins (scl1 and sda1) can be repositioned using iic1ps in sopt2. default locations are pta3 and pta2, respectively. 3 the pta4/acmp1o/bkgd/ms is limited to output only for the port i/o function. table 3. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characteri zation by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 10 3.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 table 4. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mc u is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c table 5. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 85 c maximum junction temperature t jm 95 c thermal resistance single-layer board 64-pin lqfp ja 69 c/w 80-pin lqfp 60 thermal resistance four-layer board 64-pin lqfp ja 50 c/w 80-pin lqfp 47
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 11 where: t a = ambient temperature, c ja = package thermal resist ance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices th an on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qual ification tests are pe rformed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless specified othe rwise in the device specification. table 6. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 machine series resistance r1 0 storage capacitance c 200 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ? 2.5 v maximum input voltage limit 7.5 v
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 12 3.6 dc characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 7. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 machine model (mm) v mm 200 ? v 3 charge device model (cdm) v cdm 500 ? v 4 latch-up current at t a = 85 ci lat 100 ? ma table 8. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage 1.8 3.6 v 2 c output high voltage all i/o pins, low-drive strength v oh 1.8 v, i load = ?2 ma v dd ? 0.5 ? ? v p all i/o pins, high-drive strength 2.7 v, i load = ?10 ma v dd ? 0.5 ? ? t 2.3 v, i load = ?6 ma v dd ? 0.5 ? ? c1.8v, i load = ?3 ma v dd ? 0.5 ? ? 3d output high current max total i oh for all ports i oht ??100ma 4 c output low voltage all i/o pins, low-drive strength v ol 1.8 v, i load = 2 ma ? ? 0.5 v p all i/o pins, high-drive strength 2.7 v, i load = 10 ma ? ? 0.5 t 2.3 v, i load = 6 ma ? ? 0.5 c 1.8 v, i load = 3 ma ? ? 0.5 d output low current max total i ol for all ports i olt ??100ma 5 6 p input high voltage all digital inputs v ih v dd > 2.7 v 0.70 x v dd ?? v cv dd > 1.8 v 0.85 x v dd ?? 7 p input low voltage all digital inputs v il v dd > 2.7 v ? ? 0.35 x v dd cv dd > 1.8 v ? ? 0.30 x v dd 8 c input hysteresis all digital inputs v hys 0.06 x v dd ??mv 9p input leakage current all input only pins (per pin) |i in| v in = v dd or v ss ?0.1 1 a 10 p hi-z (off-state) leakage current all input/output (per pin) |i oz| v in = v dd or v ss ?0.1 1 a 11 p pull-up resistors all digital inputs, when enabled r pu 17.5 ? 52.5 k
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 13 figure 4. pull-up and pull-down typical resistor values 12 d dc injection current 2, 3, 4 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 13 c input capacitance, all pins c in ?? 8pf 14 c ram retention voltage v ram ?0.61.0v 15 c por re-arm voltage 5 v por 0.9 1.4 2.0 v 16 d por re-arm time t por 10 ? ? s 17 p low-voltage detection threshold ? high range v lvdh v dd falling v dd rising 2.08 2.16 2.1 2.19 2.2 2.27 v 18 p low-voltage detection threshold ? low range v lvdl v dd falling v dd rising 1.80 1.88 1.82 1.90 1.91 1.99 v 19 p low-voltage warning threshold ? high range v lvwh v dd falling v dd rising 2.36 2.36 2.46 2.46 2.56 2.56 v 20 p low-voltage warning threshold ? low range v lvwl v dd falling v dd rising 2.08 2.16 2.1 2.19 2.2 2.27 v 21 p low-voltage inhibit reset/recover hysteresis v hys ?80?mv 22 p bandgap voltage reference 6 v bg 1.19 1.20 1.21 v 1 typical values are measured at 25 c. characterized, not tested 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 input must be current limited to the value specified. to determine the value of the required current-limit ing resistor, calcula te resistance values for positive and negative clamp voltages, then use the lar ger of the two values. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current great er than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples ar e: if no system clo ck is present, or if clock rate is very low (which would reduce overall power consumption). 5 maximum is highest voltage that por is guaranteed. 6 factory trimmed at v dd = 3.0 v, temp = 25 c table 8. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit pull-up resistor typicals v dd (v) pull-up resistor (k ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 c 85 c ?40 c pull-down resistor typicals v dd (v) pull-down resistance (k ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 c 85 c ?40 c 3.6
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 14 figure 5. typical low-side driv er (sink) characteristics ? low drive (ptxdsn = 0) figure 6. typical low-side driver (sink) characteristics ? high drive (ptxdsn = 1) figure 7. typical high-side (source) characteristics ? low drive (ptxdsn = 0) typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 c 85 c ?40 c 25 c, i ol = 2 ma 85 c, i ol = 2 ma ?40 c, i ol = 2 ma typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 c 85 c ?40 c 25c 85 c ?40 c typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ? v oh (v) 25 c 85 c ?40 c 25 c, i oh = 2 ma 85 c, i oh = 2 ma ?40 c, i oh = 2 ma
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 15 figure 8. typical high-side (source) characteristics ? high drive (ptxdsn = 1) 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 9. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp (c) 1 p run supply current fei mode, all modules on ri dd 25.165 mhz 3 33.4 tbd ma ?40 to 85 c t 20 mhz 28.0 tbd t 8 mhz 13.2 tbd t1 m h z 2 . 4 t b d 2 c run supply current fei mode, all modules off ri dd 25.165 mhz 3 27.4 tbd ma ?40 to 85 c t 20 mhz 22.9 tbd t8 m h z 1 1 . 3 t b d t1 m h z 2 . 0 t b d 3 t run supply current lps=0, all modules off ri dd 16 khz fbilp 3 203 tbd a ?40 to 85 c t 16 khz fbelp 154 tbd 4t run supply current lps=1, all modules off, running from flash ri dd 16 khz fbelp 350 tbd a 0 to 70 c tbd ?40 to 85 c 5 c wait mode supply current fei mode, all modules off wi dd 25.165 mhz 3 5740 tbd a ?-40 to 85 c t 20 mhz 4570 tbd t8 m h z 2 0 0 0 t b d t 1 mhz 730 tbd 6 stop2 mode supply current s2i dd n/a 3 350 tbd na 0 to 70 c p tbd ?40 to 85 c 7 stop3 mode supply current no clocks active s3i dd n/a 3 520 tbd na 0 to 70 c p tbd ?40 to 85 c typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?30 ?25 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?10 ma i oh = ?6 ma i oh = ?3 ma v dd ? v oh (v) 25 c 85 c ?40 c 25 c 85 c ?40 c
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 16 8t low power mode adders: erefsten=1 32 khz 3 500 tbd na 0 to 70 c tbd ?40 to 85 c 9 t irefsten=1 32 khz 70 tbd a 0 to 70 c tbd ?40 to 85 c 10 t tpm pwm 100 hz 12 tbd a 0 to 70 c tbd ?40 to 85 c 11 t sci, spi, or iic 300 bps 15 tbd a 0 to 70 c tbd ?40 to 85 c 12 t rtc using lpo 1 khz 200 tbd na 0 to 70 c tbd ?40 to 85 c 13 t rtc using icserclk 32 khz 1 tbd a 0 to 70 c tbd ?40 to 85 c 14 t lvd n/a 100 tbd a 0 to 70 c tbd ?40 to 85 c 15 t acmp n/a 20 tbd a 0 to 70 c tbd ?40 to 85 c 1 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. table 9. supply current characteristics (continued) num c parameter symbol bus freq v dd (v) typ 1 max unit temp (c)
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 17 figure 9. typical run i dd for fbe and fei, i dd vs. v dd (acmp and adc off, all other modules enabled) tbd
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 18 3.8 external oscillator (xosc) characteristics reference figure 10 and figure 11 for crystal or resonator circuits. table 10. xosc and ics specificati ons (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1) high range (range = 1), low power (hgo = 0) f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz 2d load capacitors low range (range=0), low power (hgo=0) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated inte rnally when range=hgo=0. 3 see crystal or resonator manufacturer?s recommendation. 3d feedback resistor low range, low power (range=0, hgo=0) 2 low range, high gain (range=0, hgo=1) high range (range=1, hgo=x) r f ? ? ? ? 10 1 ? ? ? m 4d series resistor ? low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? ? 0 100 0 0 0 ? ? ? 0 10 20 k 5c crystal start-up time 4 low range, low power low range, high power high range, low power high range, high power 4 proper pc board layout procedures must be followed to achieve specifications. t cstl t csth ? ? ? ? 200 400 5 15 ? ? ? ? ms 6d square wave input clock frequency (erefs = 0, erclken = 1) fee mode fbe or fbelp mode f extal 0.03125 0 ? ? 50.33 50.33 mhz mhz
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 19 figure 10. typical crystal or resonator circuit: high range and low range/high gain figure 11. typical crystal or resonator circuit: low range/low gain 3.9 internal clock source (ics) characteristics table 11. ics frequency specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 max unit 1p average internal reference frequency ? factory trimmed at v dd = 3.6 v and temperature = 25 c f int_ft ? 32.768 ? khz 2p internal reference frequency ? user trimmed f int_ut 31.25 ? 39.06 khz 3t internal reference start-up time t irst ?60100 s 4 p dco output frequency range ? trimmed 2 low range (drs=00) f dco_u 16 ? 20 mhz c mid range (drs=01) 32 ? 40 p high range (drs=10) 48 ? 60 5 p dco output frequency 2 reference = 32768 hz and dmx32 = 1 low range (drs=00) f dco_dmx32 ? 19.92 ? mhz p mid range (drs=01) ? 39.85 ? p high range (drs=10) ? 59.77 ? 6c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 7c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco xosc extal xtal crystal or resonator r s c 2 r f c 1 xosc extal xtal crystal or resonator
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 20 figure 12. deviation of dco output from trimmed frequency (50.33 mhz, 3.0 v) 8c total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? + 0.5 -1.0 2 %f dco 9c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 c to 70 c f dco_t ? 0.5 1 %f dco 10 c fll acquisition time 3 t acquire ?? 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 4 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 the resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f bus . measurements are made with the device powere d by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 11. ics frequency specifications (temperature range = ?40 to 85 c ambient) (continued) num c characteristic symbol min typ 1 max unit tbd
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 21 figure 13. deviation of dco output from trimmed frequency (50.33 mhz, 25 c) 3.10 ac characteristics this section describes timing charact eristics for each peripheral system. 3.10.1 control timing table 12. control timing num c rating symbol min typ 1 max unit 1d bus frequency (t cyc = 1/f bus ) v dd 2.1v v dd > 2.1v f bus dc dc ? ? 10 25.165 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 s 3 d external reset pulse width 2 t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 x t cyc ??ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 t msh 100 ? ? s 7d irq pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 2 x t cyc ? ? ? ? ns tbd
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 22 figure 14. reset timing figure 15. irq /kbipx timing 8d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 2 x t cyc ? ? ? ? ns 9c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? tbd tbd ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? tbd tbd ? ? ns 10 c stop3 recovery time, from interrupt event to vector fetch t stprec ?610 s 1 typical values are based on characterization data at v dd = 3.0v, 25 c unless otherwise stated. 2 this is the shortest pulse that is guaranteed to be recogni zed as a reset or interrupt pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lvd . 4 this is the minimum assertion time in which the interrupt may be recognized. the correct protocol is to assert the interrupt request until it is explicitly negated by the interrupt service routine. 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. table 12. control timing (continued) num c rating symbol min typ 1 max unit t extrst reset pin t ihil kbipx t ilih irq /kbipx
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 23 3.10.2 tpm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure 16. timer external clock figure 17. timer input capture pulse table 13. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 24 3.10.3 spi timing table 14 and figure 18 through figure 21 describe the timing requirements for the spi system. table 14. spi timing no. c function symbol min max unit ?d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz hz 1d spsck period master slave t spsck 2 4 2048 ? t cyc t cyc 2d enable lead time master slave t lead 1 / 2 1 ? ? t spsck t cyc 3d enable lag time master slave t lag 1 / 2 1 ? ? t spsck t cyc 4d clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns 5d data setup time (inputs) master slave t su 15 15 ? ? ns ns 6d data hold time (inputs) master slave t hi 0 25 ? ? ns ns 7 d slave access time t a ?1t cyc 8 d slave miso disable time t dis ?1t cyc 9d data valid (after spsck edge) master slave t v ? ? 25 25 ns ns 10 d data hold time (outputs) master slave t ho 0 0 ? ? ns ns 11 d rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns 12 d fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 25 figure 18. spi master timing (cpha = 0) figure 19. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 9 10 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss ( 1) (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 26 figure 20. spi slave timing (cpha = 0) figure 21. spi slave timing (cpha = 1) spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 27 3.10.4 analog comparator (acmp) electricals 3.10.5 adc characteristics table 15. analog comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dd 1.80 ? 3.6 v p supply current (active) i ddac ?2035 a d analog input voltage v ain v ss ? 0.3 ? v dd v p analog input offset voltage v aio 20 40 mv c analog comparator hysteresis v h 3.0 9.0 15.0 mv p analog input leakage current i alkg ??1 .0 a c analog comparator initialization delay t ainit ??1 .0 s table 16. 12-bit adc operating conditions c characteristic conditions symb min typ 1 1 typical values assume v ddad = 3.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment d supply voltage absolute v ddad 1.8 ? 3.6 v delta to v dd (v dd -v ddad ) 2 2 dc potential difference. v ddad -100 0 +100 mv d ground voltage delta to v ss (v ss -v ssad ) 2 v ssad -100 0 +100 mv d ref voltage high v refh 1.8 v ddad v ddad v d ref voltage low v refl v ssad v ssad v ssad v d input voltage v adin v refl ?v refh v c input capacitance c adin ?4.55.5 pf c input resistance r adin ?5 7k c analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 2 5 k external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz ? ? ? ? 5 10 8 bit mode (all valid f adck )??1 0 d adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 28 figure 22. adc input impeda nce equivalency diagram table 17. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ti ddad ? 120 ? a supply current adlpc=1 adlsmp=0 adco=1 ti ddad ? 202 ? a supply current adlpc=0 adlsmp=1 adco=1 ti ddad ? 288 ? a supply current adlpc=0 adlsmp=0 adco=1 pi ddad ?0.532 1 ma supply current stop, reset, module off i ddad ? 0.007 0.8 a adc asynchronous clock source high speed (adlpc=0) p f adack 23.35 mhz t adack = 1/f adack low power (adlpc=1) c 1.25 2 3.3 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 29 conversion time (including sample time) short sample (adlsmp=0) p t adc ? 20 ? adck cycles see the adc chapter in the mcf51qe128 reference manual for conversion time variances long sample (adlsmp=1) c ? 40 ? sample time short sample (adlsmp=0) p t ads ? 3.5 ? adck cycles long sample (adlsmp=1) c ? 23.5 ? total unadjusted error 12 bit mode t e tue ? 3.0 ? lsb 2 includes quantization 10 bit mode p ? 1 2.5 8 bit mode t ? 0.5 1.0 differential non-linearity 12 bit mode t dnl ? 1.75 ? lsb 2 10 bit mode 3 p? 0.5 1.0 8 bit mode 3 t? 0.3 0.5 integral non-linearity 12 bit mode t inl ? 1.5 ? lsb 2 10 bit mode p ? 0.5 1.0 8 bit mode t ? 0.3 0.5 zero-scale error 12 bit mode t e zs ? 1.5 ? lsb 2 v adin = v ssad 10 bit mode p ? 0.5 1.5 8 bit mode t ? 0.5 0.5 full-scale error 12 bit mode t e fs ? 1.0 ? lsb 2 v adin = v ddad 10 bit mode p ? 0.5 1 8 bit mode t ? 0.5 0.5 quantization error 12 bit mode d e q ?-1 to 0? lsb 2 10 bit mode ? ? 0.5 8 bit mode ? ? 0.5 input leakage error 12 bit mode d e il ? 2?lsb 2 pad leakage 4 * r as 10 bit mode ? 0.2 4 8 bit mode ? 0.1 1.2 temp sensor slope -40 c to 25 c d m ? 1.646 ? mv/ c 25 c to 85 c ? 1.769 ? temp sensor voltage 25cd v temp25 ?701.2? mv 1 typical values assume v ddad = 3.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table 17. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions c symb min typ 1 max unit comment
mcf51qe128 series advance information data sheet, rev. 3 electrical characteristics freescale semiconductor 30 3.10.6 flash specifications this section provides details about program/erase ti mes and program-erase endurance for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase operat ions, see the memory section of the mcf51qe128 reference manual . 3.11 emc performance electromagnetic compatibility (emc) performance is highly de pendent on the environment in which the mcu resides. board design and layout, circuit topology choices, location and charact eristics of external components as well as mcu software operation all play a significant role in emc performance. the sy stem designer should consult fr eescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. table 18. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase -40 c to 85 cv prog/erase 1.8 3.6 v d supply voltage for read operation v read 1.8 3.6 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz d internal fclk period (1/fclk) t fcyc 56 . 6 7 s p longword program time (random location) (2) t prog 9t fcyc p longword program time (burst mode) (2) t burst 4t fcyc p page erase time 2 2 these values are hardware state machi ne controlled. user code doe s not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p mass erase time (2) t mass 20,000 t fcyc longword program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measur ed at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. r iddbp ?9.7?ma page erase current 3 r iddpe ?7.6?ma c program/erase endurance 4 t l to t h = ?40 c to + 85 c t = 25 c 4 typical endurance for flash was evaluated for this product family on th e hc9s12dx64. for additional information on how freescale defines typical endurance, plea se refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles c data retention 5 5 typical data retention values are based on intrinsic capability of th e technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional informat ion on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
electrical characteristics mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 31 3.11.1 radiated emissions microcontroller radiated rf emissions ar e measured from 150 khz to 1 ghz usi ng the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurem ent is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two pack age orientations (north and east). the maximum radiated rf emissi ons of the tested configuration in all orientations are less than or equal to the reported emissions levels. 3.11.2 conducted transient susceptibility microcontroller transient conducted suscepti bility is measured in accordance with an internal freescale test method. the measurement is performed with the microc ontroller installed on a custom emc eval uation board and running specialized emc test software designed in compliance with the test method. the conducted susceptibility is determined by injecting the transien t susceptibility signal on each pin of the microcontroller. the transient waveform and injection methodology is based on iec 61000-4-4 (eft/b). the transient voltage requ ired to cause performance de gradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below table 20 . table 19. radiated emi ssions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on qualification test results. unit radiated emissions, electric field v re_tem v dd = tbd t a = +25 o c package type tbd 0.15 ? 50 mhz tbd crystal tbd bus tbd db v 50 ? 150 mhz tbd 150 ? 500 mhz tbd 500 ? 1000 mhz tbd iec level tbd ? sae level tbd ? table 20. conducted susceptibility, eft/b parameter symbol conditions f osc /f bus result amplitude 1 (min) 1 data based on qualification test re sults. not tested in production. unit conducted susceptibility, electrical fast transient/burst (eft/b) v cs_eft v dd = tbd t a = +25 o c package type tbd tbd crystal tbd bus a tbd kv b tbd c tbd d tbd
mcf51qe128 series advance information data sheet, rev. 3 ordering information freescale semiconductor 32 the susceptibility perf ormance classification is described in table 21 . 4 ordering information this section contains ordering information for mcf51qe128 and MCF51QE64 devices. 5 package information the below table details the various packages available. 5.1 mechanical drawings the following pages are mechanical draw ings for the packages described in table 23 . for the latest available drawings please visit our web site ( http://www.freescale.com ) and enter the package?s document nu mber into the keyword search box. table 21. susceptibility performance classification result performance criteria a no failure the mcu performs as designed during and after exposure. b self-recovering failure the mcu does not perform as designed during exposure. the mcu returns automatically to normal operati on after exposure is removed. c soft failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until expo sure is removed and the reset pin is asserted. d hard failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is remo ved and the power to the mcu is cycled. e damage the mcu does not perform as designed during and after exposure. the mcu cannot be returned to proper operation due to physical damage or other permanent performance degradation. table 22. ordering information freescale part number 1 1 see the reference manual, mcf51qe128rm , for a complete description of modules included on each device. memory package 2 2 see table 23 for package information. flash ram mcf51qe128clk 128k 8k 80 lqfp mcf51qe128clh 64 lqfp MCF51QE64clh 64k 4k 64 lqfp table 23. package descriptions pin count package type abbreviation designator case no. document no. 80 low quad flat package lqfp lk 917a 98ass23237w 64 low quad flat package lqfp lh 840f 98ass23234w
package information mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 33 figure 23. 80-pin lqfp package dr awing (case 917a, doc #98ass23237w) 1 20 21 40 41 60 61 80 view aa ??? ??? ab view y (k) (z) (w) view aa dim a min max min max inches 14.00 bsc 0.551 bsc millimeters a1 7.00 bsc 0.276 bsc b 14.00 bsc 0.551 bsc b1 7.00 bsc 0.276 bsc c ??? 1.60 ??? 0.063 c1 0.04 0.24 0.002 0.009 c2 1.30 1.50 0.051 0.059 d 0.22 0.38 0.009 0.015 e 0.40 0.75 0.016 0.030 f 0.17 0.33 0.007 0.013 g 0.65 bsc 0.026 bsc j 0.09 0.27 0.004 0.011 k 0.50 ref 0.020 ref p 0.325 bsc 0.013 ref r1 0.10 0.20 0.004 0.008 s 16.00 bsc 0.630 bsc s1 8.00 bsc 0.315 bsc u 0.09 0.16 0.004 0.006 v 16.00 bsc 0.630 bsc v1 8.00 bsc 0.315 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref 0 01 ??? ??? 02 c2 c1 c l 0 10 0 9 14 0 10 0 9 14 l?m 0.20 (0.008) h n 4x 3x view y ?l? l?m 0.20 (0.008) t n ?m? b v v1 b1 ?n? s1 a1 s a 4x 20 tips seating 0.10 (0.004) t ?h? plane ?t? 8x c 2 gage 0.25 (0.010) plane 2x r r1 e 1 s 0.05 (0.002) ab ?x? x= l, m, n p g plating base metal j u f d section ab?ab s l?m m 0.13 (0.005) n s t rotated 90 clockwise case 917a-02 issue c date 09/21/95
mcf51qe128 series advance information data sheet, rev. 3 package information freescale semiconductor 34 figure 24. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 1 of 3
package information mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 35 figure 25. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 2 of 3
mcf51qe128 series advance information data sheet, rev. 3 package information freescale semiconductor 36 figure 26. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 3 of 3
product documentation mcf51qe128 series advance information data sheet, rev. 3 freescale semiconductor 37 6 product documentation find the most current versions of all documents at: http://www.freescale.com 7 revision history to provide the most up-to-date information, the revision of our documents on the world wide we b are the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes changes contained in this document. reference manual (mcf51qe128rm) contains extensive product information including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information. table 24. revision history revision date description of changes 2 22 may 2007 initial advance information release. 3 25 jun 2007 ta b l e 8 : changed condition entires in specs #6 (v ih ) and #7 (v il ) from v dd 1.8v to v dd > 2.7v and v dd 1.8v to v dd >1.8v. ta b l e 8 : changed v dd rising and v dd falling min/typ/max specs in row #19 (low-voltage warning threshold?high range) from 2.35 , 2.40, and 2.50 to 2.36, 2.46, and 2.56 respectively.
document number: mcf51qe128 rev. 3 06/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved.

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